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Title of the paper: A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function Available at: https://ieeexplore.ieee.org/document/8009192 |
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Temporal majority voting (TMV) and bit masking were used in previous works to identify and store the location of unstable or marginally stable SRAM cells. However, TMV requires a long test time and significant hardware resources. In addition, the number of repetitive power-ups required to find the most stable cells is prohibitively high. To overcome the shortcomings of TMV, we propose a novel data remanence based technique to detect SRAM cells with the highest stability for reliable key generation. This approach requires only two remanence tests: writing ‘1’ (or ‘0’) to the entire array and momentarily shutting down the power until a few cells flip. We exploit the fact that the cells that are easily flipped are the most robust cells when written with the opposite data. The proposed method is more effective in finding the most stable cells in a large SRAM array than a TMV scheme with 1,000 power-up tests. Experimental studies show that the 256-bit key generated from a 512 kbit SRAM using the proposed data remanence method is 100% stable under different temperatures, power ramp up times, and device aging.
Introduction
(good introduction, the authors distinguish between “strong” and “weak” PUFs)
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Testbed: off-the-shelf SRAM chips from Microchip Technology
The first step is to determine the appropriate power down time. If the power down time is too long, then the data stored in the array is completely collapsed and the SRAM will power up to its uninitialized state.
The SRAM chips we tested were fabricated in an ultra-low leakage technology, requiring a relatively long power down time to observe data remanence effects. We expect a much shorter data remanence time (e.g. microseconds) for SRAMs built in advanced CMOS technologies.
→ The overall data remanence trends will be agnostic to the technology node.
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the cells start to flip after a power down period of about 130ms. When the power down period increases to about 600ms, the flip ratio reaches 50% which corresponds to the SRAM power up state.
In short, compared to TMV, the proposed technique requires not only fewer power-ups (hundreds or thousands → 2) but also shorter power down periods (600ms → 200ms) which significantly reduces the overall test time.
Depending on the number of stable cells we want to select, the amount of data remanence needs to be tuned accordingly by changing the power off period.
if we want to sort the cells from strongest ‘0’ to balanced ‘0’, we first write data ‘1’ to the whole array and sweep the power down period from 100ms to 600ms for the SRAM chips used in our experiment.
When applying the data remanence method to generate stable keys, we only select the strongest cells.
Depending on how many stable bits we want to select, we can vary the power off period. For example, for a 256-bit key, we select roughly 128 stable ‘0’s and 128 stable ‘1’s from 512 kbit cells. The power off period should be around 185ms.
To determine the 256 most stable bits from a 512 kbit SRAM array using TMV, which is only 256/512k = 0.05%, we may need millions of repetitive power up tests for TMV, which is impractical.
In a realistic scenario, we can select more bits than we need and then pick the number of stable bits requested by our target application.
Note that we perform this extensive test on one of the chips to determine the appropriate power down period of all chips.
An attractive feature of the data remanence test is that it can be performed at any temperature.
The top 0.05% stable cells found from the power down sweep test will remain stable at different temperatures and voltage conditions.
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SRAM PUF MEASUREMENT RESULTS
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