wang22systematic

Introduction

Physical Unclonable Function (PUF)

What is PUF?

• PUF is a die-specific random function or a silicon biometric, which can generate a unique predetermined response to an applied stimulus or challenge.

• The uniqueness of many PUF designs is derived from the variations that occur during the fabrication process in a completely unintentional, random and uncontrollable manner.

Why do we need PUF?

• These unique responses can be used as key generation and authentication in hardware security application.

• Compared with the alternative of storing the random response information in non-volatile memory, PUFs
  provide more resilient resistance to physical attack since the information will disappear during power off. Moreover, the response from each PUF is unique, ideally even for copies of the same design in different dies.

SRAM-based PUFs

What are SRAM PUFs?

• They exploit the power-up value of cells to provide the PUF response, with the corresponding address serving as the challenge.

• The information stored in SRAM cells is unpredictable when the array is first powered on without any preceding write operation, because the state stored in the SRAM cells will be decided by the
  relative the strength of the two back-to-back inverters in the SRAM cells.

• Ideally, the two inverters in each cell are identical, but in practice they will be slightly different in unpredictable ways because of random process variations (unique to each copy of the circuit) caused by random-dopant fluctuations, line-edge roughness, etc.

Main Pros and Cons of SRAM PUFs

• Pros: SRAMs are widely employed in many system-on-chips (SoCs), which make the implementation of SRAM PUF simple and require no additional design processes.

• Cons: reliability of the SRAM cells:

  1. The power-up state in SRAM cells is highly sensitive to the noise and temperature/voltage variation, i.e. 5–10 percent of cells are unstable and do not power up to the same consistent value during multiple power-up cycles.

  2. Aging degradation affects the threshold voltage of MOSFETs and can change the relative strengths of the two inverters in a cell, resulting in a change in the power-up state.

Why reliability is important?

• In order to exploit the start-up value of the SRAM cells to perform some cryptography function
  (i.e., key generation), the response or start-up value for each SRAM cell should be highly reliable under different operating conditions (i.e., different temperature or voltage) with a bit-error-rate (BER) close to 0

→ The BER has to reach a reasonable level before SRAM has been deployed as a PUF

How to increase the reliability of the SRAM PUF? (state-of-the- art approaches)

Several mechanisms have been proposed to reduce cell instability and increase the reliability of SRAM PUFs:

Error Correction Codes (ECC)

• Error Correction Codes (ECC) is a conventional approach to enhance the reliability of SRAM PUF with the target bit error rate less than 1e–6.

• The overall methodology is divided into two steps: enrollment and regeneration.

  • During the enrollment, the ECC will perform the encoding by using a larger amount of raw (unstable) data from the SRAM array. The output of encoding will be the secret key and help data. The help data is public information and can be stored in any non-volatile memory.

  • During the regeneration phase, the user will exploit the help data and the new regenerated raw (noisy) PUF data to recover the secret key.

• In order to successfully recover the secret key in the field, the raw PUF data size and help data will be much larger than the size of the secret key.

• The ECC implementation will generally introduce a significant hardware overhead.

Preselection

• The preselection scheme filters out the unstable cells leaving behind only stable cells as the PUF output.

• In this way, the final PUF output will be virtually 100% reliable and the bit-error rate will approach zero. At the same time, the over-all hardware overhead is negligible since only the address of the selected cell requires to be stored in nonvolatile memory.

• Neighbor Analysis: To identify stable SRAM PUF cells, the researchers in previous work exploit the spatial correlation of the SRAM PUF cells indicating the higher likelihood of the most stable cells to be surrounded by the stable cells. However, this selection method still requires high-temperature/low voltage (HTLV) and low-temperature/low voltage (LTLV) to perform the enrollment test, which will increase both the test time and the cost.

• Changing the structure of the SRAM cell: Some researchers propose a revised design of the SRAM cells to fulfill the selection of the strong cells. The theory behind this approach is to introduce a skew or tilt to the cells through the revised structure of the SRAM cells. If the natural mismatch of a cell is larger than the introduced tilt, the cell will not change the value before or after introducing the tilt and will be considered as a strong cell for the PUF application. However, this selection method requires the modification of traditional SRAM cells, which will increase design costs and limit the range of application.

• Data Remanence Approach: A remanence-based method has been proposed to evaluate the strength of the SRAM PUF. A value of either a ‘1’ or ‘0’ will first be written to the SRAM cells followed by turning off the power for a very brief controlled period. Thereafter, the cell is powered back on to observe the value. If the cell flips the value that has been written in previously to the cell, it will be considered as a strong PUF cell. However, the selection method requires precise control of the power-off time. This may present implementation challenge for advanced CMOS technology.

Hardening

Reverse burn-in aging has been applied to the SRAM cells to strengthen the response of cells.

Contributions and goal of this paper

The method proposed in this paper to increase reliability of SRAM PUF

• This work is an extension of a previous work https://ieeexplore.ieee.org/document/8349685, where a preselection method is proposed by only controlling the V_DD voltage and not the power-off time as in the data remanence approach.

• In this recent paper, the authors consider also the impact of temperature, voltage variation, and aging effect.

Their contributions include:

1. A discussion of the start-up behavior of the SRAM cell and a detailed analysis of the ramp rate effect.

2. Proposal for a comprehensive methodology to perform preselection of the strong stable SRAM cells.

3. Presentation of the corresponding data from silicon experiments, including performing voltage and tem-
   perature variation and aging experiments to validate the reliability of the selected SRAM cells.

The main objective of this paper is to show that the proposed bit selection method can reliably select the strongest SRAM cells for PUF application. The details of implementation (overhead, power consumption et al.) will greatly depend on the real-world application, such as the memory type, the manufacturing technology, how the memory is tested-externally or with on-board memory BIST, and many other variables. These optimizations are left to be addressed by the SoC designer.