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To guarantee SRAM PUF reliability, state-of-the-art articles use ECC (fuzzy extractor) and/or pre-selection techniques /wiki/spaces/SaraPhD/pages/2338717699 :

  1. ECC

    1. A Robust SRAM-PUF Key Generation Scheme Based on Polar Codes

    2. https://www.sciencedirect.com/science/article/pii/S0026269220304432

  2. Pre-selection

    1. alheyasat19weak

    2. https://link.springer.com/article/10.1007/s10207-023-00668-0

    3. https://www.sciencedirect.com/science/article/pii/S0167926018304747

    4. https://link.springer.com/article/10.1007/s41635-017-0012-3

  3. Both: ECC+preselection

    1. A Proof of Concept SRAM-based Physically Unclonable Function (PUF) Key Generation Mechanism for IoT Devices

  4. Modified SRAM design

    1. Analysis and reduction of SRAM PUF Bit Error Rate

    2. https://www.mdpi.com/2079-9268/7/1/2

  5. Improving reliability through power-up control

    1. Power-up control techniques for reliable SRAM PUF

Both of these methods require using NVM memory to store the calculated helper-data (memory-map resp).

Memory-map can be generated at each time → should be the same

In fact using a pre-selection method is good to distinguish between bits used as RNG and PUF, but this requires lots of computations, to obtain an RNG using a hash function with any bunch of bits is sufficient.

Interesting Facts

  • helper data is public and can be stored on a remote server, see https://link.springer.com/article/10.1007/s10207-023-00668-0 where the protocol is explained, they used the fact of turning off the power for a short time after putting all the values to 1, but with some change in the hardware design of the SRAM memory → ECC+pre-selection

  • Power-up control techniques for reliable SRAM PUF → The authors propose simple power-up control schemes to improve the reproducibility of SRAM PUFs that can be fully integrated on chip, and confirm their effectiveness both in simulation and measurements. In this section, two power-up sequence control techniques are proposed: 1) utilizing the characteristics of the transistors in the sub-threshold region, and 2) manipulating the voltage ramp-up speed during the power-up sequence. Both techniques minimize the effect of circuit noise on the evaluation process and achieve an optimal operating point in terms of PUF cell reliability.

  • A good and brief review of the different methods of error reduction from the state-of-the-art is included in https://www.mdpi.com/2079-9268/7/1/2 , a good explanation of voting methods is also offered. The authors propose a enhanced voting mechanism.

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