Paris SCuM boards
- Sara Faour
Tested SCuM chips
The 5V booting mode follows the connections described in
Remark: connection for chips with ID starting with S such as “S15” have different pins order
Relevant links:
ID | Booting & Printing | Booting Mode (1.8V/5V) | Tested by | Last testing date | Notes | Did it ever boot? (from Berkeley spreasheet) | |
|---|---|---|---|---|---|---|---|
| 1 | L12 |
| 5 V | @Sara Faour | Apr 22, 2025 |
| (tap) |
| 2 | L34 |
| 5 V | @Sara Faour | Apr 22, 2025 |
| (tap) |
| 3 | L45 |
| 5 V | @Sara Faour | Apr 22, 2025 |
| (cold boot?) |
| 4 | M34 |
| 5 V | @Sara Faour | Apr 22, 2025 |
| |
| 5 | M38 |
| 5 V | @Sara Faour | Apr 22, 2025 |
| |
| 6 | M39 | 5 V | @Fil Maksimovic | Apr 22, 2025 |
|
| |
| 7 | M41 | 5 V | @Fil Maksimovic | Apr 22, 2025 |
| ** | |
| 8 | M42 |
| 5 V | @Sara Faour | Apr 22, 2025 |
| ** |
| 9 | M43 |
| 5 V | @Sara Faour | Apr 22, 2025 |
|
|
| 10 | M44 | 1.8 V | @Fil Maksimovic | Apr 22, 2025 |
|
| |
| 11 | M45 |
| 5 V | @Sara Faour | Apr 22, 2025 |
| ?? **** |
| 12 | M46 |
| 5 V | @Sara Faour | Apr 22, 2025 |
|
|
| 13 | M49 |
| 5 V | @Alexandre Abadie | Apr 18, 2025 |
|
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| 14 | M50 |
| 5 V | @Sara Faour | Apr 22, 2025 |
|
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| 15 | S15 | 5 V | @Fil Maksimovic | Apr 22, 2025 |
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| |
| 16 | S17 | 5 V | @Fil Maksimovic | Apr 22, 2025 |
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| 17 | S18 | 5 V | @Fil Maksimovic | Apr 22, 2025 |
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| 18 | S19 | 5 V & 1.8 V | @Fil Maksimovic | Apr 22, 2025 |
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| 19 | S20 | 5 V | @Fil Maksimovic | Apr 22, 2025 |
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** according to my previous notes: Hard reset (GPIO 13) does not go low after bootload, but HCLK (GPIO 2) and 3wb lines (GPIO 8, 9, 10) look good. SCuM boots if it just gets 1.8 V from nRF and bypasses the 1.1 V and 1.8 V regulators on Sulu
**** Hard reset (GPIO 13) does not go low after bootload, but HCLK (GPIO 12) and 3wb lines (GPIO 8, 9, 10) look good. SCuM boots if it just gets 1.8 V from nRF and bypasses the 1.1 V and 1.8 V regulators on Sulu. Clock is weird, problem may be in the external DC-DC converter, which should be bypassed