SRAM PUF Reliability

To guarantee SRAM PUF reliability, state-of-the-art articles use ECC (fuzzy extractor) and/or pre-selection techniques https://crystalfree.atlassian.net/wiki/spaces/SaraPhD/pages/2338717699 :

1. ECC

   1. Polar codes: A Robust SRAM-PUF Key Generation Scheme Based on Polar Codes

   2. based on Hashing and BCH: Lightweight (Reverse) Fuzzy Extractor with Multiple Referenced PUF Responses

   3. BCH: Open-Source Software-Based SRAM-PUF for Secure Data and Key Storage Using Off-The-Shelf SRAM | TU Delft Repository

   4. Repetition code: A Microcontroller SRAM-PUF

   5. HC (Hamming Code) / Golay2412 (corrects up to 3 errors for each 12 bits) / Repetition Code: PUF for the Commons: Enhancing Embedded Security on the OS Level

2. Pre-selection

   1. alheyasat19weak

   2. Error reduction of SRAM-based physically unclonable function for chip authentication

   3. A reliable PUF in a dual function SRAM

   4. Systematic Correlation and Cell Neighborhood Analysis of SRAM PUF for Robust and Unique Key Generation

   5. one VDD/temperature measure: A Method to Improve Reliability in a 65-nm SRAM PUF Array

   6. Fourier analysis: A Novel Security Key Generation Method for SRAM PUF Based on Fourier Analysis

   7. according to MF and SD: Estimation during Design Phases of Suitable SRAM Cells for PUF Applications Using Separatrix and Mismatch Metrics

3. Both: ECC+preselection

   1. A Proof of Concept SRAM-based Physically Unclonable Function (PUF) Key Generation Mechanism for IoT Devices

4. Modified SRAM design (hardening)

   1. Analysis and reduction of SRAM PUF Bit Error Rate

   2. https://www.mdpi.com/2079-9268/7/1/2

   3. hardening +ECC: https://www.sciencedirect.com/science/article/pii/S0026269220304432 → Typical constructions comprise a repetition code (C rep) followed by a Reed-Muller code (RM) to obtain a failure rate P_fail <10⁻⁶.

   4. hardening +ECC: A 0.19pJ/b PVT-Variation-Tolerant Hybrid Physically Unclonable Function Circuit for 100% Stable Secure Key Generation in 22nm CMOS

   5. new SRAM design + ECC: An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9 Key Error Probability

5. Improving reliability through power-up control

   1. Power-up control techniques for reliable SRAM PUF

Both of these methods require using NVM memory to store the calculated helper-data (memory-map resp).

Memory-map can be generated at each time → should be the same

Interesting Facts

• helper data is public and can be stored on a remote server, see https://link.springer.com/article/10.1007/s10207-023-00668-0 where the protocol is explained, they used the fact of turning off the power for a short time after putting all the values to 1, but with some change in the hardware design of the SRAM memory → ECC+pre-selection

Open

• Power-up control techniques for reliable SRAM PUF → The authors propose simple power-up control schemes to improve the reproducibility of SRAM PUFs that can be fully integrated on chip, and confirm their effectiveness both in simulation and measurements. In this section, two power-up sequence control techniques are proposed: 1) utilizing the characteristics of the transistors in the sub-threshold region, and 2) manipulating the voltage ramp-up speed during the power-up sequence. Both techniques minimize the effect of circuit noise on the evaluation process and achieve an optimal operating point in terms of PUF cell reliability.

Open

• A good and brief review of the different methods of error reduction from the state-of-the-art is included in https://www.mdpi.com/2079-9268/7/1/2 , a good explanation of voting methods is also offered. The authors propose a enhanced voting mechanism.