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Introduction

The goal of the Single Chip micro Mote project is to develop a complete self-contained wireless sensor node on a single chip, including sensing, computation, communication, and power, with no external components. SCµM-3C is an important step along that path, containing everything needed for sensing, computation, and communication. This includes a 32 bit Cortex M0 processor, 2.4 GHz radio transceiver, and both a temperature sensor and a lighthouse location sensor. With a printed solar cell and battery, SCµM3C
would satisfy the project goal.

Quick Start & Resources

Check the pdf.

Chip Overview

• SCµM-3C is a 3x2x0.3 mm³ silicon chip made in the TSMC 65nm LP RF MS CMOS process. It contains approximately 8 million transistors. SCµM-3C has 64 kB of program SRAM memory (IMEM) and 64 kB of data SRAM memory (DMEM). There are also 16 kB of program ROM which contain a bootloader.

• The process does not offer any writable non-volatile storage, so every time that power is removed from the chip, both the program and data are lost.

• Loading program memory can be done either optically or via a wired connection. Once program memory is loaded, the chip needs to be configured for the desired functionality.

• Configuration bits are controlled with a combination of the Analog Scan Chain (ASC) and Memory Mapped Registers (MMR).

Analog Scan Chain

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The Analog Scan Chain

• Changing configuration with the ASC requires that the entire desired sequence of bits be shifted into position and then loaded in parallel into control registers for the various operational units on the chip.

• This process can be accomplished either from off-chip through six pads, or via software on the microprocessor. By default, the processor is in control of the ASC.

• Programming the ASC requires several milliseconds, a faster control mechanism is provided via memory mapped registers. Often the control authority selection between ASC and MMR is yet another ASC bit.

Memory Mapped Registers

ANALOG_CFG_REG__# actually points to two separate registers depending on whether you are reading or writing:

1. If you write to that memory mapped register then you are setting bits in what is called the analog_cfg bus.

2. If you read the value from ANALOG_CFG_REG__#, you are not reading the current value of analog_cfg but rather a separate bus called analog_rdata.

Example: to read the RSSI value per the source verilog, in auxdig.c:

Pads

Check the pdf for further details about the different pads.

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Die photo of SCM-3C with pad labels. Dimensions are 3mm ×
2mm × 0.3mm.

• Most of the East and West pads are for debugging purposes. One notable exception is the antenna pad on the West side, labeled RF INPUT. For size-constrained applications, this can be wire bonded to any floating pad on the chip, such as ASC_PHI1.

• The minimum number of pads that must be connected to boot the mote is two: VBAT and GND. For roughly half of the chips, the optical boot sequence described below will work with just these two pins connected. For the other half, VDDD_LDO_OUT must be briefly raised to VBAT in order for the chip to boot.

• For wired bootloading, the minimum number of pads is six: VBAT, VDDIO, GND, and the three wire bus: BOOT_3WB_CLK, BOOT_3WB_DATA, and BOOT_3WB_LATCH.

Voltage Domains

There are eight different voltage domains and five different bandgap references feeding them.

PCB Overview

• The SCM chips are packaged into QFN-100 packages from Quik-Pak to make them replaceable, reduce the board cost (relaxed trace/space), and to speed up board assembly.

• The boards are powered via the 5V USB connection and a 1.5V LDO is included to generate VBAT for SCM. The FTDI UART/USB chip generates a 3.3V supply internally which can be used for VDDIO. A zero-ohm jumper on the board determines whether VDDIO on SCM is connected to the 3.3V or 1.5V supply domain.

• The Teensy header and ASC level shifters are not used since the analog scan chain can be controlled from the Cortex on chip and optical bootload is easier than wired programming.

Bootloading

There are two bootload modes: optical and wired. The mote defaults to optical bootload mode which requires no external connections.

Both optical and wired programming use a Teensy 3.6 for the programmer.

Optical Bootloading

Check the pdf for further details about the installation…

• The programmer will send a preamble to allow the on-chip receiver to settle, then send a start symbol, followed by dummy data to wait for hard reset to execute, and then the binary program data encoded with 4B/5B.

• The on-chip optical receiver will wait to recognize the start symbol and will issue a hard reset to get the chip to re-execute its ROM. The receiver will then decode the data, convert it to the same format as 3-wire bus, and load the program data into SRAM.

• The programmer provides the option of whether or not to issue a hard reset to the chip prior to bootloading. For including a hard reset, the start symbol is the sequence [169 176 167 50]. For skipping the hard reset the start symbol is [184 84 89 40]. If the reset is skipped then no dummy data is sent.

3-Wire Bus Bootloading

• The BOOTLOAD_SOURCE_SELECT pin is used to switch the mote to wired mode. This pin is internally pulled to ground selecting optical mode, and should be driven high (either to VDDD or VBAT) to select wired boot mode.

• The clock, data, latch, and hard reset pins should be connected to their respective pins on SCM.

• Level-shifters are not required for clock, data, and latch on 3C whereas they were on earlier versions. The hard reset pin on SCM however will not tolerate 3.3V so either a level shifter is required or the Teensy should be configured as an open drain output for that pin.

Mote Startup

When the mote first boots up it executes the following steps from ROM:

• Set BOOT MODE to 3wb

• Assert GPIO-0 high

• Wait until 64 kB have been written to IMEM via 3wb interface

• Set BOOT MODE to none (regular execution)

• Switch instruction execution from ROM to RAM

• Issue a soft reset

A useful troubleshooting step for debugging startup is to see if GPIO-0 is high. If it is then the mote is likely waiting to be bootloaded. If not, then something went wrong with the startup process.
Other useful debug steps are to check that HCLK is coming out GPIO-12 and that both hard GPIO-13 and soft GPIO-14 resets are high.

Optical Boot Troubleshoot

Check the pdf for further details.

It is possible to adjust the pulse width parameters that the Teensy uses when flashing the programming LED. The figure above shows the parameters that are used to set the on and off times for one and zero data bits. These values are passed to the Teensy in the bootloader script using the command ’configopt’ followed by four integer values. These values are used as a for loop index that ultimately determines how wide each pulse is. The values {80,80,3,80} were determined experimentally to work relatively well.

Misc Optical Bootload Related Items

Optical Data Transfer

The optical receiver also provides a mechanism for wirelessly sending data to the mote after it has been programmed. Bits received over optical are clocked into a 32-bit shift register and an interrupt called “optical_irq_in” is asserted every 32 new bits. A SFD (start frame delimiter) of [221 176 231 47] is also available to help synchronize the mote to the data sequence to be transferred. When the 32-bit register matches this value, a separate interrupt called “optical_sfd_interrupt” is asserted. By first waiting for the
SFD interrupt and then reading the new data every time the “optical_irq_in” IRQ executes, one can send commands or transfer arbitrary amounts of data to the mote and have it stored in DMEM.
analog_rdata[335:304] = Optical 32-bit Register

Optical Timing Transfer

Bootloading provides an opportunity to also provide initial timing calibration that can be accomplished by sending the optical SFD sequence at a fixed rate after bootload has completed.

Lighthouse Localization Receiver

The optical receiver on SCM can also be used at limited range to receive localization pulses from a HTC Lighthouse.

Future Feature Ideas

• Hardware IDs & Calibration Data

• RF Bootloader

GPIO

Control

In the scum-test-code repo are several functions and variables for controlling the GPIOs. Functions include:

• GPO control. This function sets the GPIO banks. It takes four unsigned char arguments, each setting the banks for groups of four GPOs. For example GPO control(1, 2, 8, 5); sets GPOs 0-3 to bank 1, GPO 4-7 to bank 2, GPO 8-11 to bank 8, and GPO 12-15 to bank 5.

• GPI control.

• GPO enables and GPI enables. These functions enables the GPOs and GPIs respectively. Each function takes a 16-bit integer, where each 1 bit enables the corresponding GPIO and each 0 bit disables the corresponding GPIO. For example, GPO enables(0xF00F); enables GPOs 0-3 and GPOs 12-15.

GPO control and GPO enables both change the analog scan chain (ASC), so don’t forget to load changes by calling:

See the pdf for a detailed matlab code on setting the GPIO direction control.

Interrupts

There are four external interrupts available in the GPIO bank with various trigger polarities and debouncing. All four are synchronized to HCLK.
EXT_INTERRUPT<0> is debounced, and is active high
EXT_INTERRUPT<1> is not debounced, and is active high
EXT_INTERRUPT<2> is not debounced, and is active low
EXT_INTERRUPT<3> is not debounced, and is active low
The order of the interrupt mask is as follows, ordered from LSB to MSB. For example, to activate only the UART and RFTIMER ISRs the mask would be 0x0081.
UART
interrupt_gpio3_activehigh_debounced
optical_irq_in
ADC
0
0
RF_FSM
RFTIMER
interrupt_rawchips_startval
interrupt_rawchips_32
0
optical_sfd_interrupt
interrupt_gpio8_activehigh
interrupt_gpio9_activelow
interrupt_gpio10_activelow
0

UART

UART is the primary debugging method, all printf output is printed out over UART. The baud rate should be adjusted accordingly to HCLK since the divide ratio is fixed. Other settings that should be used: 8 data bits, 1 stop bit, and no parity.
Terminal

This terminal program is useful for passively monitoring debug output from the chip as well as sending commands over UART. It is also possible to both send and receive UART data from Python or MATLAB.

Clocks

From power-on to until the ASC bits for the crossbar are set, all of the clocks are sourced from LF CLOCK. After the ASC initialization, HCLK and RFTIMER are usually derived from HF CLOCK. The CLK 2MHz is the chip clock for SCµM and is usually derived from RC 2MHz.

Frequency Counters

Timers

Note the design assumption that HCLK and RFTIMER are phase aligned. This means that both clocks should be derived from the same oscillator and that HCLK must be an integer multiple of RFTIMER.

Temperature

The SCµM development boards have a rather large thermal mass due the large ground plane, so the ramp rate should be aroud 1.5^◦C/min or less to minimize hysteresis.

The frequencies of both of the 2 MHz and the 32 kHz RC oscillators have a non-linear relationship with temperature, but the ratio of their two frequencies is linear with respect to temperature. Using the frequency counters for the 2 MHz and the 32 kHz oscillators, we can estimate the ambient temperature after a two-point temperature calibration.

LO, PA, and Divider Hardware Details

Analog Scan Chain

This section describes the functionality of the chain bits.

Cortex Code

This section describes some of the very low-level functions for directly controlling parts of the transmitter from the cortex.

Common Configurations

This section describes the necessary scan/Cortex procedure to use the radio in various modes.

• Receive Mode (RF only)

• Transmit Mode - 802.15.4

• Transmit Mode - BLE

Power On Control

• There are four separate LDOs in the transceiver: the LO, PA, divider, and IF.

• The possible ways to turn on an LDO are: scan chain, GP input, hardware FSM control, and through memory mapped registers from the Cortex-M0 (available in 3C only).

Digital Baseband

• Various debugging signals are available for output via the GPIO bank.

• Reset can come from either analog scan chain or a memory mapped register and is active low.

• An estimate of received signal quality can be obtained by reading the Link Quality Indicator (LQI) and RSSI registers.

• By keeping track of how many extra samples are added or dropped over the course of the packet, an estimate of the difference between the TX and RX chip rates can be obtained.

Sensor ADC

This subsystem has several mutually exclusive purposes which can be chosen by modifying analog scan chain settings:

• Interface to an external sensor whose output is an analog voltage

• Battery voltage monitor

• Temperature sensor

Triggering A Measurement

All of the methods described below rely on a command sent over UART, but the low-level way of triggering a reset relies on the memory-mapped register ADC_REG_START. Setting this to 0x1 primes the ADC for reading. If the on-chip FSM is used to control the ADC, one only needs to wait until the ADC-related interrupt is triggered. Otherwise, some software to control the ADC will be necessary.

On-Chip FSM

This uses a memory-mapped register to start the taped-out finite state machine. The simplest way of starting a conversion is by feeding SCM the appropriate command over UART. The function sensor_adc/adc.py/test_adc_spot() can do this by setting control_mode to ‘uart’.

GPIO Loopback

This uses software (i.e. the Cortex M0) to step the ADC through its various states rather than relying on the on-chip FSM to step the ADC. Function sensor_adc/adc.py/test_adc_spot() can do this by setting control_mode to ‘loopback’.

Reading the Output

Memory-Mapped Register

Whenever the on-chip interrupt indicating that the subsystem has completed its measurement is triggered, the result of that measurement is contained in memory-mapped register ADC_REG__DATA (you can find this in Memory_Map.h).

The simplest way of retrieving this value upon the interrupt’s trigger is by having SCM print the register’s value to UART. This is what the current ISR does, and function sensor_adc/adc.py/test_adc_spot() can read that by setting read_mode to ‘uart’.

802.15.4 Radio Demo Software

The goal of the radio demo software was to validate the board support package (BSP) software development for eventual integration with OpenWSN.

• CRC Check

• Initialize Analog Scan Chain

• Optical Calibration

• Building a Channel Table (appropriate LO settings for all channels need to be found)

• Acquiring Packet Rate (The mote begins listening on channel 11 and assumes that an OpenMote is sending 20B packets at a rate of 8 Hz. After SCM hears an appropriate packet on the channel it is listening to, then it will begin using its timers to attempt to turn its radio on and off in sequence with the OpenMote)

• Frequency Management (The mote needs to make sure its RX ADC clock is the correct frequency since the chip clock is derived from this clock source)

• BSP-like Radio Control (An attempt was made to implement the radio control in a manner which
  facilitates BSP development for OpenWSN)

• Hard-Wired Radio Connection

BLE

Bluetooth Low Energy (BLE) allows SCµM to interface with phones and other common devices that do not support 802.15.4. There are three BLE channels: channel 37 (2.402 GHz), channel 38 (2.426 GHz), and channel 39 (2.480 GHz).

Sweeping the fine codes allows SCµM to transmit BLE packets with the same coarse and mid codes for a range of around ±10 ◦C from the temperature at calibration.

Important terms

• LDO regulator: low drop-out regulator

• 3wb: 3-wire bus

• ESD: electrostatic discharge

• ISER: Interrupt set enable reg

• TIA: transimpedance amplifiers

• RSSI: received signal strength indication

• CDR: clock and data recovery

• PGA: programmable gain amplifier

• PTAT: proportional to absolute temperature

• FSM: finite state machine

• BSP: board support package

• PDU: protocol data unit

• LFSR: Linear Feedback Shift Register

• GFSK: Gaussian frequency shift keying modulation

• ASIC: application-specific integrated circuit

Google search

• A bandgap voltage reference is a temperature independent voltage reference circuit widely used in integrated circuits. It produces a fixed (constant) voltage regardless of power supply variations, temperature changes, or circuit loading from a device.

• Electroless nickel immersion gold (ENIG or ENi/IAu), also known as immersion gold (Au), chemical Ni/Au or soft gold, is a metal plating process used in the manufacture of printed circuit boards (PCBs), to avoid oxidation and improve the solderability of copper contacts and plated through-holes.

• SMA (SubMiniature version A) connectors are semi-precision coaxial RF connectors.

• An interrupt request (IRQ) is an asynchronous signal sent from a device to a processor indicating that in order to process a request, attention is required.

• Differential nonlinearity (acronym DNL) is a commonly used measure of performance in digital-to-analog (DAC) and analog-to-digital (ADC) converters. It is a term describing the deviation between two analog values corresponding to adjacent input digital values.

• INL - Integral Non-Linearity: DNL errors accumulate to produce a total Integral Non-Linearity (INL). It is defined as the maximum deviation from the ideal slope of the ADC and is measured from the center of the step.

References for further details

• See Appendix B in [3] for hardware details on the on-chip optical receiver

• See [4] for details on the 3-wire bus mode

• See [4] for further details on debugging startup

• See Section 3.35 in [4] for a detailed description of the RFTIMER module.

• LO, PA, and Divider Hardware Details Adapted from the appendix of Fil Maksimovic [2]

• Use instructions in [4] to load and transmit a packet 802.15.4

[1] David Burnett. Crystal-free wireless communication with relaxation oscillators and its applications. PhD thesis, PhD thesis, EECS Department, University of California, Berkeley, 2019.
[2] Filip Maksimovic. Monolithic Wireless Transceiver Integration. PhD thesis, PhD thesis, EECS Department, University of California, Berkeley,2018.
[3] Bradley Wheeler. Low Power, Crystal-Free Design for Monolithic Receivers. PhD thesis, PhD thesis, EECS Department, University of California, Berkeley, 2019.
[4] Sahar Mesri. Design and user guide for the single chip mote digital system. Master’s thesis, EECS Department, University of California, Berkeley, 5 2016.
[5] Joseph Yiu. The Definitive Guide to ARM Cortex-M0 and Cortex-M0+ Processors. Academic Press, 2015.
[6] M. D. Scott, B. E. Boser, and K. S. J. Pister. An ultralow-energy adc for smart dust. IEEE Journal of Solid-State Circuits, 38(7):1123–1129, 7 2003.