Attendees

@Thomas Watteyne
@Austin Patel
@Kristofer PISTER
@David Burnett
@Alex Moreno
@Andrew Fearing
@Fil Maksimovic
@Mina Rady

Updates

@Austin Patel
- @Joshua Alexander picking up 2 boards
- motes → quik-pak → Digicom (Mo’s)
- next is to verify all works without pins attached
- verify whether any bubbling present
- unclear whether we had a photo of the quik-pak’ed modules
- Mo indicated he would use a lower-temp solder; he indicated he uses some “shielding” (when attaching surface-mount components?)
@Joshua Alexander confirms he will be able to test boards today
@Kristofer PISTER opaque epoxy has a higher temperature, putting it on the wirebonds but leaving the centre of the chip without epoxy may be possible
@Andrew Fearing points at https://www.qptechnologies.com/services/ic-assembly/encapsulation-options/
@Fil Maksimovic
- trying to find the root cause of SCuM not be able to transmit to nRF: tone separation error, or chipping clock
- using divided LC for the chipping clock, there is a 400ppm swing between “0’s” and “1’s”?
- with access to GPIOs, would be easier, chip used is not wire-bonded completely
@David Burnett
- looking at what probe station and wire bonder within driving distance
@Thomas Watteyne
- https://tnano.org/2021/10/special-section-on-nanoscale-computing-communication-and-applications-nanococoa-2021/ deadline Mar 31, 2022
@Mina Rady
- PhD thesis defended Dec 9, 2021
- Manuscript: Agile Multi-PHY Wireless Networking
- some interesting deliverables:
  - g6TiSCH firmware: how to custom build your g6TiSCH/6DYN network? https://github.com/minarady1/openwsn-fw/tree/develop_FW-891
  - RPLSim: yet another RPL simulator: a lightweight discrete event RPL simulator in Python
    - Allowed us to answer the question "how to optimize for time-to-first-death"? (specially using multi-PHY integration)
    - Life-OF
    - Example configuration: run using a single-PHY network MRHOF and compare it to a multi-PHY network using Life-OF.